This invention is related to my co-pending application entitled, "High Resolution Frequency Synthesizer", Ser. No. 79,603, filed on Sept. 27, 1979. In particular, this invention is directed to a phase lock loop applicable to the frequency synthesis techniques disclosed in that co-pending application. In my co-pending patent application, a system is disclosed having a center frequency and a programmable finite pull-in and holding range. The pull-in and holding range is the same and requires no filters.
In conventional phase lock loop circuitry (PLL), pull-in and holding ranges are different. Therefore, such circuitry generally requires the use of filters within the loop. The present invention removes such a requirement.
In the co-pending application, the reference oscillator and clock filter are not affected in the circuitry. Accordingly, there are multiple phase lock loops on the same reference clock without affecting each other and they may be maintained in an edge synchronous manner to the reference clock frequency. Accordingly, the jitter and the output frequency remain the same over the entire PLL range. It is of course a function of the reference clock frequency. This is contrasted with standard PLL technology where jitter becomes extremely large with large frequency division.
As a result, resolution can be controlled within very narrow limits even when the ratio of the output frequency to the synchronization frequency is at extremes, whether they be large or small. Moreover, a known time base repetitive pulse may be used for alignment of frequency even when the ratio of frequency to time base pulse is exceptionally large. Such technique is useful in time division multiple access (TDMA) applications where a large frame length is used and a large number of frequencies must be adjusted due to doppler effect of satellite movement and the stability of the reference frequency.